One of the main technologies for ultra large-scale integrated (ULSI) circuits is complementary metal-oxide-semiconductor (CMOS) technology. High-performance CMOS technologies commonly employ various processes to form offset spacers, sidewall spacers, and silicide. Offset spacers are used to place shallow source/drain extensions and/or halo implants a specific distance from a gate edge. Offset spacers have been used for several other types of implant processes, such as xenon pre-amorphization implants, for example. Typically, offset spacers consist of silicon oxide or silicon nitride.
The width of offset spacers has been varied to adjust the channel lengths of the P-channel MOS (PMOS) and N-channel MOS (NMOS), as well as to reduce the overlap capacitance, known as the Miller capacitance, between the gate electrode and the source/drain region. While increasing the widths of the offset spacers decreases the overlap between the source/drain extensions and the gate, thus reducing the Miller capacitance and improving device performance, if the offset spacers are too wide, a condition referred to as “under-lap” occurs. With under-lap, the source/drain extensions no longer reach the gate and device performance degrades. Conversely, if the offset spacers are narrower than expected, excessive direct overlap will reduce the metallurgical channel length, resulting in degraded gate control of the channel and thus reduced Vt, degrading the phenomenon commonly referred to as “Vt roll-off.” Hence, it is important to precisely control the width of the offset spacers during device manufacturing.
CMOS technologies regularly employ both NMOS and PMOS transistors within the same overall device. The PMOS and NMOS transistors utilize different dopant materials for source/drain and source/drain-extension implantation. During the thermal annealing required for dopant activation, the dopant, such as boron, used in the P-type implanted source/drain extension areas diffuses much more than the larger arsenic atoms employed in the extension areas of the NMOS transistors. As a result, the PMOS source/drain extension areas will have a larger overlap with the PMOS gates than will be the case with source/drain extensions and NMOS gates. When the width of the offset spacers are the same, the faster diffusion of the boron atoms creates problems in preventing a large overlap in the source/drain extension areas of the PMOS transistor, and for preventing under-lap in the source/drain extension areas of the NMOS transistors. This necessitates the use of lower doses PMOS transistors in source-drain extensions compared to those in NMOS transistors. For example, it is not at all uncommon for the extension dose of a PMOS transistor to be half of that in an NMOS. The reduced dose results in increased series resistance and reduced drive current, an inherent trade-off with different optimal points for NMOS and PMOS respectively. To overcome this problem, differential widths for the offset spacers of the NMOS devices and PMOS devices have been provided. There is a need for forming offset spacers in a production-worthy manner that is also able to form differential width offset spacers.
Among the steps employed for manufacturing semiconductor processes are etching and deposition. A number of different etching technologies and methods available, including plasma etching and several types of ion beam etching. In certain instances, over etching, e.g., etching for an extended period of time compared to the normal etching period, has been used to reduce feature sizes. However, over etching creates a microloading effect. Maintaining uniformity is of particular importance during etching processes. Uniformity refers to the evenness of etching for critical dimension, as well as uniformity of etching across a wafer and from wafer to wafer. At the microscopic level, etching rates and profiles depend on feature sizes and feature separation. Microscopic uniformity problems can be grouped into several categories including pattern-dependent etch effects, generally referred to as microloading. More specifically, microloading refers to the dependence of the etch rate on feature separation for identically sized features and results from the depletion of reactants when the wafer has a local, higher-density area. In conventional offset spacer fabrication techniques, the same size offset spacers are produced where the critical dimension (CD) of features are provided as well as for those features where CD is greater. In other words, the same size offset spacers are employed regardless of the CD of the polysilicon feature. Creating wider offset spacers for the polysilicon features with a smaller CD would result in improved less rapid reduction of threshold voltage at smaller gate lengths, i.e. it would alleviate the short-channel effect commonly referred to as Vt roll-off. In other words, the contribution of across chip line width variation (ACLV) to Vt roll-off and chip quiescent current (IDDQ) would be reduced.